// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details

`timescale 1ns / 1ps
`default_nettype wire  
`include "debugfpga_version.vh"
  
  module BncSecondary
   (
    input  iRst_n,                                         //asynch active-low reset 
    
    input  iClk_2M,                                        //core-clock 2MHz
    input  iClk_20M,                                       //clock @ 20MHz
       
    //DEBUG
    input       iFmPldRev_n,
   
    //LED Status & Control
    input       iPltRstCpu0,
    input [7:0] iMainRev,
    input [7:0] iMainTestRev,
    input [7:0] iScmRev,
    input [7:0] iScmTestRev,
    input [7:0] iStatusLED,
    input       iScmBmcAuxPwrFlt,
    input       iScmAuxPwrFlt,
    input       iCpuAuxPwrFlt,
    input       iBmcPwrFlt,
    input       iPfrOverride_n,
    input [4:0] iMasterCode,
    input [2:0] iPsuFltCode,
    input       iP5VMainPwrFlt,
    input [7:0] iBiosPostCode,
    input [7:0] iPfrPostCode_n, 
    input [5:0] iCpu0DimmFltCode,
    input [5:0] iCpu1DimmFltCode,
    input [7:0] iCpu0FltCode,
    input [7:0] iCpu1FltCode,
    input [7:0] iLedCpu0DimmCh1_8Flt,
    input [7:0] iLedCpu1DimmCh1_8Flt,
    
    
    output oLedCtrl0,
    output oLedCtrl1,
    output oLedCtrl2,
    output oLedCtrl3,
    output oLedCtrl4,
    output oLedCtrl5,
    output oLedCtrl6,
    output oLedCtrl7,
    
    output oFmPost7Seg1Sel_n,
    output oFmPost7Seg2Sel_n,
    output oFmPostLedSel,
    
    output oFmCpu0DimmFaultLedSel0,
    output oFmCpu0DimmFaultLedSel1,
    output oFmCpu1DimmFaultLedSel0,
    output oFmCpu1DimmFaultLedSel1,
    
    //MISC CTRL & STATUS SIGNALS
    input  iFmPmbus2MuxSelFpga,
    output oFmPmbus2MuxSel,

    input  iFmCpu0GlbRstWarn_n,
    output oFmCpu0GlbRstWarn_n,
	
    input  iAuxPwrgdCpu0,
    output oFmCpu0PartitionId
	
    );
   
   
   //--------------------------------
   //Local Parameter declarations
   
   localparam SGPIO_MAIN2MOD = 20;
   
    `ifdef SIMULATION
        localparam  T_12_5mS_2M  =  11'd1000;
    `else
        localparam  T_12_5mS_2M  =  19'd25000;
    `endif
   
   //--------------------------------
   //WIRE declarations

   //SGPIO   
   wire [(SGPIO_MAIN2MOD*8)-1:0] wIPData;
   wire [(SGPIO_MAIN2MOD*8)-1:0] wOPData;

   wire                          wStandAloneMode_n;
   wire                          w4S_8SMode_n;
   wire                          wNodeID0;
   wire                          wNodeID1;

   wire                          wDualPartition_n;
   wire                          wPartitionSel;
   wire                          wIsModular;
   wire                          wPltRstCpu0;
   wire                          wBmcOnctlSync_n;

   wire [7:0]                    wMainRev;
   wire [7:0]                    wMainTestRev;
   wire [7:0]                    wScmRev;
   wire [7:0]                    wScmTestRev;
   wire [7:0]                    wStatusLED;
   wire                          wScmBmcAuxPwrFlt;
   wire                          wCpuAuxPwrFlt;
   wire                          wScmAuxPwrFlt;
   wire                          wBmcPwrFlt;
   wire                          wPfrOverride_n;

   wire                          wUpiInitDone;

   wire [4:0]                    wMasterCode;
   wire [2:0]                    wPsuFltCode;
   wire                          wP5VMainPwrFlt;

   wire [7:0]                    wBiosPostCode;
   wire [7:0]                    wPfrPostCode_n;

   wire [5:0]                    wCpu0DimmFltCode;
   wire [5:0]                    wCpu1DimmFltCode;

   wire [7:0]                    wCpu0FltCode;
   wire [7:0]                    wCpu1FltCode;

   wire [7:0]                    wFpgaCode1;
   wire [7:0]                    wFpgaCode2;

   wire [7:0]                    wLedCpu0DimmCh1_8Flt;

   wire [7:0]                    wLedCpu1DimmCh1_8Flt;

   wire                          wCpu0CatErr;
   wire                          wCpu1CatErr;
   wire                          wCpu0ThermtripLatched;
   wire                          wCpu1ThermtripLatched;
   wire                          wSpeakerBmc;
   wire                          wSkt0Fault;
   wire                          wSkt1Fault;

   wire [7:0]                    wLED_CONTROL;

   wire                          wEna1ms;

   wire                          wRstPltrstSyncPfrOutAck_n;
   wire                          wBmcOnctlAck_n;
   wire                          wHPfrEna;
   wire                          wLegacyNode;
   wire                          wPfrGlobalAck;
   wire                          wModularPrsnt;
   wire                          wSMRJODone;
   
   wire                          wDone12_5msTimer;
   wire                          wAUX_PWRGD_CPU0_FF;
   
   //--------------------------------
   //Internal Instances


   //Post Code
   postcode_fub postcode
     (
      .iClk                       (iClk_2M),                            //clock for sequential logic 
      .iRst_n                     (iRst_n),                             //reset signal from PLL Lock, resets state machine to initial state
      //Master 
      .iMASTER_POST_CODE          (iMasterCode),                        //Master Sequence State post-code, from CPU FPGA thru sGPIO
      //SCM_AUX
      .iSCM_BMC_AUX_PWR_FAULT     (iScmBmcAuxPwrFlt),                   //SCM side AUX power fault info, from CPU FPGA thru sGPIO
      .iSCM_PWR_FAULT             (iScmAuxPwrFlt),
      .iBMC_PWR_FAULT             (iBmcPwrFlt),
      //CPU_AUX
      .iCPU_AUX_PWR_FLT           (iCpuAuxPwrFlt),                      //no actual CPU_AUX power error code in PPO
      //PSU_MAIN
      .iP5V_MAIN_PWR_FAULT        (iP5VMainPwrFlt),                     //SCM side main power fault info, from CPU FPGA thru sGPIO
      .iPSU_FLT_CODE              (iPsuFltCode),                        //MB PSU FLT CODE, from CPU FPGA thru sGPIO
      //CPU_MAIN
      .iCPU0_FLT_CODE             (iCpu0FltCode),                       //CPU0 MAIN POWER FLT CODE, from CPU FPGA thru sGPIO
      .iCPU1_FLT_CODE             (iCpu1FltCode),                       //CPU1 MAIN POWER FLT CODE, from CPU FPGA thru sGPIO
      //MEM
      .iCPU0_DIMM_FLT_CODE        (iCpu0DimmFltCode),                   //DIMM FLT CODE, from CPU FPGA thru sGPIO
      .iCPU1_DIMM_FLT_CODE        (iCpu1DimmFltCode),                   //DIMM FLT CODE, from CPU FPGA thru sGPIO  
      
      .oDisplay1                  (wFpgaCode1),
      .oDisplay2                  (wFpgaCode2)
      );


   //This is used for the Led Control block as a 500Hz clock signal
   ClkDiv #(.DIV(4000))   //based on a 2MHz clock this will deliver a 1msec (1KHz) periodic enable signal
   ClkLC
      (
       .iClk(iClk_2M),
       .iRst_n(iRst_n),
       .div_clk(wEna1ms)
       );
   

   //LED_CONTROL
   led_control
	 #(.DBGFPGAREV(`DEBUG_MAJOR_VERSION), .DBGFPGATEST(`DEBUG_MINOR_VERSION))
   led_control_inst
     (
      .iClk                         (iClk_2M),                          //clock for sequential logic 
      .iRst_n                       (iRst_n),                           //reset signal from PLL Lock, resets state machine to initial state
      
      .iCPUFPGAREV                  (iMainRev),                         //CPU FPGA version, from CPU FPGA thru sGPIO
      .iCPUFPGATEST                 (iMainTestRev),                     //CPU FPGA test version, from CPU FPGA thru sGPIO
      .iSCMFPGAREV                  (iScmRev),                          //SCM FPGA version, from CPU FPGA thru sGPIO
      .iSCMFPGATEST                 (iScmTestRev),                      //SCM FPGA test version, from CPU FPGA thru sGPIO
      
      .iENA                         (wEna1ms),                          //Enable signal, used to run at slower freq
      
      .iRST_PLTRST_CPU0_PLD_R_N     (iPltRstCpu0),                      //PLTRST_N signal from CPU FPGA thru sGPIO (used to automatically switch from FPGA to BIOS postcodes in displays)
      
      .iSTATUS_LED                  (iStatusLED),                       //input to be reflected at status LEDs from sGPIO when oStatusLedSel is asserted
      .oSTATUS_LED_SEL              (oFmPostLedSel),                    //output generated by this module to select when STATUS LEDs should take into account the LED_CONTROL output pins
      
      .iFPGA_POST_CODE1             (wFpgaCode2),                       //Main Fpga postcode for 7-segment display 1 (MSB) before PLT_RST_N is deasserted (already encoded into 7-Seg Display)
      .iFPGA_POST_CODE2             (wFpgaCode1),                       //Main Fpga postcode for 7-segment display 2 (LSB) before PLT_RST_N is deasserted (already encoded into 7-Seg Display)
      .iBIOS_POST_CODE              (iBiosPostCode),                    //Port 80 post-codes from BIOS for the 2 7-Segment displays, after PLT_RST_N is deasserted
      .iPFR_POST_CODE               (iPfrPostCode_n),                   //PFR postcode to be displayed on 7-segment display 1 (MSB), by asserting PFR override signal (overriding Fpga & BIOS post-codes)
      .iPFR_OVERRIDE_N              (iPfrOverride_n),                   //PRF override signal, comming from CPU FPGA thru sGPIO, if asserted, PRF postcode data is displayed in 7-segment displays, otherwise, FPGA or BIOS postcodes will be displayed depending on RST_PLTRST_N signal
      .oPOST_CODE_SEL1_N            (oFmPost7Seg1Sel_n),                //to latch LED_CONTROL outputs into the 7-segment display1 (MSB) (active low)
      .oPOST_CODE_SEL2_N            (oFmPost7Seg2Sel_n),                //to latch LED_CONTROL outputs into the 7-segment display2 (LSB) (active low)
      
      .iLED_CPU0_DIMM_CH1_8_FLT     (iLedCpu0DimmCh1_8Flt),             //input for the Cpu0 Dimms 1(for 1DPC) CH 1-8 Fault LEDs indications
      .oLED_CPU0_DIMM_CH1_8_FLT_SEL (oFmCpu0DimmFaultLedSel0),          //to latch LED_CONTROL output into CPU0 Dimms 1(for 1DPC) CH 1-8 Fault LEDs
      
      .iLED_CPU0_DIMM_CH9_12_FLT     (4'h0),                            //input for the Cpu0 Dimms 1(for 1DPC) CH 9_12 Fault LEDs indications, only 4 channels valid
      .oLED_CPU0_DIMM_CH9_12_FLT_SEL (oFmCpu0DimmFaultLedSel1),         //to latch LED_CONTROL output into CPU0 Dimms 1(for 1DPC) CH 9_12 Fault LEDs
      
      .iLED_CPU1_DIMM_CH1_8_FLT      (iLedCpu1DimmCh1_8Flt),            //input for the Cpu1 Dimms 1(for 1DPC) CH 1-8 Fault LEDs indications
      .oLED_CPU1_DIMM_CH1_8_FLT_SEL  (oFmCpu1DimmFaultLedSel0),         //to latch LED_CONTROL output into CPU0 Dimms 1(for 1DPC) CH 1-8 Fault LEDs
      
      .iLED_CPU1_DIMM_CH9_12_FLT     (4'h0),                            //input for the Cpu1 Dimms 1(for 1DPC) CH 9_12 Fault LEDs indications, only 4 channels valid
      .oLED_CPU1_DIMM_CH9_12_FLT_SEL (oFmCpu1DimmFaultLedSel1),         //to latch LED_CONTROL output into CPU0 Dimms 1(for 1DPC) CH 9_12 Fault LEDs
      
      .iPLD_REV_N                    (iFmPldRev_n),                     //when asserted (active low) will show CPU/SCM/Debug FPGA versions in 7-Segment Displays 2&1
      
      .oLED_CONTROL                  (wLED_CONTROL)                     //output of the mux to all LEDs resources
      
      );
   
   assign oLedCtrl0 = wLED_CONTROL[0];
   assign oLedCtrl1 = wLED_CONTROL[1];
   assign oLedCtrl2 = wLED_CONTROL[2];
   assign oLedCtrl3 = wLED_CONTROL[3];
   assign oLedCtrl4 = wLED_CONTROL[4];
   assign oLedCtrl5 = wLED_CONTROL[5];
   assign oLedCtrl6 = wLED_CONTROL[6];
   assign oLedCtrl7 = wLED_CONTROL[7];
   
   assign oFmPmbus2MuxSel            = iFmPmbus2MuxSelFpga;

   assign oFmCpu0GlbRstWarn_n        = iFmCpu0GlbRstWarn_n;

   GlitchFilter2 #(.NUMBER_OF_SIGNALS(1), .RST_VALUE(1'b0))
   partition_id_filter
     (
      .iClk(iClk_2M),
      .iARst_n(iRst_n),
      .iSRst_n(1'b1),
      .iEna(1'b1),
      .iSignal({iAuxPwrgdCpu0
	      }),
      .oFilteredSignals({wAUX_PWRGD_CPU0_FF
		       })
      );
	  
   // Delay 12.5 ms after CPU_AUX_PWRGD is asserted
   delay #(.COUNT(T_12_5mS_2M)) 
       Timer12_5ms(
           .iClk    ( iClk_2M            ),
           .iRst    ( iRst_n             ),
           .iStart  ( wAUX_PWRGD_CPU0_FF ),
           .iClrCnt ( 1'b0               ),
           .oDone   ( wDone12_5msTimer   )
       );
   
   
   assign oFmCpu0PartitionId = wAUX_PWRGD_CPU0_FF && wDone12_5msTimer ? 1'bZ : 1'b0 ;
   
endmodule // BncSecondary



